A Field-Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after being manufactured. The FPGA configuration is generally specified using a hardware description language (HDL). Contemporary FPGAs have large resources of logic gates and random access memory (RAM) blocks to implement complex digital computations. FPGAs typically contain programmable logic components called “configurable logic blocks” (CLB) or “logic array blocks” (LAB), and a network of reconfigurable interconnects that allow the blocks to communicate with each other. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.
An application circuit can be mapped into an FPGA provided that adequate resources are available. While the number of CLBs/LABs and I/Os required can be readily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. For example, implementing a crossbar switch typically requires much more routing resources than a systolic array of the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs.
The FPGAs contain various computing elements that communicate with each other in performing operations where the signals are sent over routing channels composed of wires. Interconnect routing switches (primarily implemented as static multiplexers) allow for high-speed communications over long distances. Indeed, such interconnect routing switches often comprise the majority of the silicon area on a FPGA and can be very power hungry. Static multiplexers are used within the interconnects to switch signals between wires. In operation, the majority of static multiplexers are idle in a configured FPGA.
Generally, static multiplexers are devices that can select one of several input signals and forward the selected input to a single line output. In many applications, multiplexers are used to allow multiple signal sources to communicate over the same channel, although only one source may communicate at a time. A 4-input static multiplexer is illustrated in FIGS. 1A-C. The multiplexer 100 has four inputs 102 and four select bits 106 that can be used to select the output 104. FIGS. 1B and 1C illustrate two implementations of the multiplexer 100 where the select functions are implemented either with a positive trigger 112 (implementation 110) or with an inverted negative trigger 122 (implementation 120), respectively.
Typically, an inverter is placed at the output of the multiplexer to improve the signal driving capability of the multiplexer. A 4 input static multiplexer utilizing an inverter is illustrated in FIGS. 1D-E. The multiplexer 130 includes inputs 132 and four separate select bits 134, where only one of the select bits is allowed to turn on and pass an input that is inverted using an inverter 136 resulting in the output 138. FIGS. 1D and 1E illustrate two implementations of multiplexer 130 where the select functions are implemented either with a positive trigger in 140 or with an inverted negative trigger in 150, respectively. The implementation 150 illustrates an inverter 152 where the inverter can be supplied by a lower supply voltage (VDDL) 154 relative to a higher supply voltage (VDDH) 156 driving the memory cells of the select bits. Generally, driving memory cells at a slightly higher supply voltage (VDDH) while having the logic inverters and/or buffers at a lower supply voltage (VDDL) can improve performance and reduce power consumption.
When executing mapped designs, an FPGA can often have unused resources, resulting in current leakage. To alleviate the problem of leakage in both the CLB/LAB and the interconnect network, the unused blocks can be power gated to turn off their circuitry when not being utilized. Power gating can be achieved by adding a footer transistor that turns off the block during power gating mode (i.e. “sleep” mode). A 4-input static multiplexer with an output inverter and power gating is illustrated in FIGS. 2A-C. The multiplexer 200 includes a power gating enable signal input 202 that is turned on (or off depending on the implementation) during power gating mode. Traditionally, power gating utilizes a footer transistor 222 that is relatively large in size (compared to the size of output inverter transistors) that is stacked with the inverter transistor 224 as illustrated in FIG. 2C.